In the fabrication of semiconductor devices, a mask is drawn after the design layout thereof is modified by optical proximity correction (OPC), which is a technique of predicting distortions due to the optical proximity effect and compensating for the distortions. Design features are transferred to a wafer by exposure using the drawn mask. Note that the OPC-corrected layout may be directly drawn on a wafer without using a mask.
OPC is intended to correct distortions which are caused not only in photolithography, but also in other processes, such as charged particle beam lithography, X-ray lithography, etching, chemical mechanical polishing (CMP), mask formation, etc.
In general, there is a trade-off between the accuracy of OPC and the manufacturing cost of a mask, a wafer, etc. In other words, more accurate OPC tends to result in higher cost.
Conventionally, as a technique of the OPC process, rule-based OPC has been mainly used. In rule-based OPC, correction rules are described by a human based on geometric elements which are those that are handled by a design rule checker (DRC). Also, the unit of a correction step, the sub-division level of a target to be corrected, the correction level of a corner portion, the correction level of a line end portion, etc. are parameters for improving accuracy. As the accuracies of these parameters are increased, the OPC processing time and the mask manufacturing cost increase.
In recent years, model-based OPC has been employed instead of rule-based OPC. In model-based OPC, correction is performed while predicting features formed on a wafer using lithography simulation. Therefore, more accurate correction can be achieved, but a longer processing time is required because the simulation is performed at the chip level. For example, when conventional process resources are used, several days or weeks may be required. The unit length in the length direction of an edge to be moved, the number of the units, the step of movement, etc. are parameters for improving accuracy. As the accuracies of these parameters are increased, the number of portions of data to be drawn as well as resources required for the OPC process tends to increase, resulting in an increase in the mask manufacturing cost.
In general, model-based OPC produces an OPC-corrected layout having a more complicated feature than that of rule-based OPC, and therefore, the amount of out data increases. Therefore, it takes a longer time to convert the OPC-corrected layout into mask data and draw the mask on a wafer.
As described above, in both rule-based OPC and model-based OPC, as the accuracy of the OPC process is increased, the OPC processing time and the mask manufacturing cost increase.
On the other hand, as microfabrication technology has been advanced, there has been a demand for a feature area per unit area and a feature circumferential length which are limited to predetermined ranges in order to ensure the process dimension accuracy and the flatness of lithography, dry etching, CMP, etc. For example, in the case of the step of forming a gate electrode of a transistor, this is achieved by providing, in addition to the gate electrode of the transistor, a dummy feature which is not directly involved in the operation of the transistor. Such a dummy feature needs to be modified using the OPC process in terms of ensuring the process dimension accuracy and the flatness, and therefore, the OPC processing time and the mask manufacturing cost further increase.
In this situation, International Publication No. WO 2006/118098 describes a technique of separating, in features laid out throughout a semiconductor chip, blocks in which the OPC process is performed with high accuracy (e.g., blocks including transistors etc. which actually operate as a circuit) and blocks in which the OPC process is performed with low accuracy (blocks in which variations in feature formation have less influence on circuit operation (e.g., a dummy feature)). When the high-accuracy OPC process is performed, the finished feature formed on the wafer has a high accuracy. However, the number of geometric elements calculated in the OPC process and the number of geometric elements formed in the OPC process are several times or dozens of times as large as when the low-accuracy process is performed. Therefore, by reducing to the extent possible the blocks in which the high-accuracy OPC process is performed, the OPC processing time and the mask manufacturing cost are reduced.
Japanese Patent Publication No. 2003-114515 describes a technique of using a dummy feature in order to reduce or prevent variations in dimensions in a circuit feature depending on the layout of a mask feature. In particular, the dummy features are arranged so that the feature footprint ratio and the feature circumferential length per unit area meet standards.
Japanese Patent Publication No. H09-311432 describes a dummy feature having substantially the same line width as a representative line width of an original feature for configuring a circuit etc. As a result, substantially a uniform feature density can be achieved, thereby making it possible to reduce or prevent variations in dimensions due to a non-uniform feature density.